Intel Quartus Prime Professional Edition 18.0 What’s New in Intel® Quartus® Prime Design Software v18.0 Intel® Quartus® Prime software v18.0 has improvements made across the three key areas that designers care about the most—performance, productivity, and usability. Check out the following new training courses and collateral: What's New In Intel Quartus Prime Software v18.0 training AN 307: Intel FPGA Design Flow for Xilinx* Users Learn how to estimate power with the new Early Power Estimator video The Intel Quartus Prime Pro Edition Handbook is now subdivided into more manageable user guides, they can be found on the Support page. You can select the topic of interest to see all the relevant documents associated with that topic. Performance Intel Stratix® 10 GX, SX, TX, and MX Device Support Intel Quartus Prime Pro Edition software v18.0 supports Intel Stratix® 10 TX, MX, SX, and GX devices. Intel Stratix 10 GX devices are designed to meet the high-performance demands of high-throughput systems with up to 10 TFLOPS of floating-point performance and transceiver support up to 28.3 Gbps for chip-module, chip-to-chip, and backplane applications. Intel Stratix 10 SX SoCs feature a hard processor system with a 64 bit quad-core ARM* Cortex*-A53 processor available in all densities in addition to all the features of Intel Stratix 10 GX devices. The Stratix 10 SoC FPGA Hardware Overview training has been updated to contain information on booting and configuration. A section on board design guidelines has also been added to help ensure your early design planning results in a successful implementation. Intel Stratix 10 TX devices deliver the most advanced transceiver capabilities in the industry by combining H-Tile and E-Tile transceivers. The E-Tile provides dual-mode transceiver capabilities, allowing a single transceiver channel to operate up to 58 Gbps in PAM-4 mode or 30 Gbps in non-return-to-zero (NRZ) mode. Intel Stratix 10 TX FPGAs also support the other breakthrough innovations of the Intel Stratix 10 GX and SX variants. Intel Stratix 10 MX devices combine the programmability and flexibility of Intel Stratix 10 FPGAs and SoCs with the 3D stacked high-bandwidth memory 2 (HBM2) in a single package. Intel Stratix 10 MX FPGAs support both H-Tile and E-Tile transceivers. Learn more with the updated training class on High Bandwidth Memory Interfaces in Intel Stratix 10 MX Devices: Introduction & Architecture. With the revolutionary Intel Hyperflex™ FPGA Architecture, Intel Stratix 10 devices deliver performance gains over previous-generation high-performance FPGAs. Learn more about the Intel Hyperflex FPGA Architecture and Intel Stratix 10 devices. Watch all the latest Intel Stratix 10 FPGA videos on the Intel Stratix 10 Demo Videos page. To learn how to leverage the Intel Hyperflex FPGA Architecture features, watch the new short videos on the Intel Quartus Prime software support page. Productivity Compile Time You can now accelerate FPGA development with faster compile times of your Intel Stratix 10 designs in v18.0 as compared to prior releases. Larger Intel Stratix 10 designs show greater compile time reduction. There are additional settings on how to reduce compile time that you can refer to in the Compiler User Guide. Memory Reduction - User Designs With Intel Quartus Prime Pro Edition software v18.0, designs will now experience significant reduction in peak virtual memory requirements as compared to the 17.1.1 release. All Intel Stratix 10 designs compile in less than 64GB of memory space. Concurrent Analysis Concurrent analysis support provides the ability to analyze results of your design while compilation is running. This feature is supported with Timing Analyzer, Netlist Viewers, and compilation reports, enabling you to get your design completed much faster. Understand further details about concurrent analysis. Partial Reconfiguration Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. With Intel Quartus Prime Pro Edition software v18.0, key enhancements include: Push button partial reconfiguration design flow for faster time to market Optimized Intel Stratix 10 device partial reconfiguration time Intel Stratix 10 device support for Traditional and Hierarchical partial reconfiguration flows Learn more about each of these features on the Partial Reconfiguration page. Rapid Recompile Intel Stratix 10 device rapid recompile support Signal Tap logic analyzer support for Intel Stratix 10 device rapid recompile Intel Stratix 10 device post-fit incremental route Signal Tap logic analyzer support Learn more on the Rapid Recompile page.